Memory controllers are a common feature in connection with computing devices. Among the functions of memory controllers are interface timing, refresh generation, arbitration and access to a memory component. Memory controllers may also allocate and control access to memory provided for the purpose of buffering data or as a data cache in connection with exchanges of data between a first interface or channel and a second interface or channel.
As the clock speeds of computer processors and data busses have increased, the need for fast external memory has also increased. However, the speed of such memory has been unable to keep pace with increases in the speed of computer processors and data busses. For example, commonly available bulk memory has data rates of 100 or 133 Megabytes per second, while processors, and other components within a typical computer have data rates of 200 Megabytes per second or more. Accordingly, external memory used to buffer data or as a data cache has become an increasingly large impediment to increased computer peripheral performance.
Although certain types of memory, such as SRAM, is capable of providing memory bandwidths that are closely matched to that of high speed processors, such memory is typically provided as an integral part of an associated processor. In addition, such memory is typically relatively small in capacity. Furthermore, such memory is generally considered prohibitively expensive to provide in the quantities required by a typical external memory application.
One approach to increasing the bandwidth of memory is to use memory having a data bus width that is greater than the width of the bus or busses interconnected to the memory. However, this approach results in increased cost and complexity, and can result in memory chips having an unacceptably large number of pins.
Memory controllers that include data compression and decompression engines and that allow data to be saved in compressed or uncompressed formats in the system memory are known. Such systems allow data to be passed among components of the system in compressed form, thereby decreasing the amount of time required to transfer the data. Such a system is discussed in U.S. Pat. No. 6,173,381 (the “'381 patent”). However, the '381 patent does not disclose a method and apparatus for increasing the data throughput performance of a memory controller that does not require modifications to the host computer system. Instead, the '381 patent discusses compressing data to improve the efficiency with which that data is moved around the associated system. Accordingly, in connection with providing compressed data to a hard drive or other storage device, the '381 patent contemplates transferring that data in compressed form and storing the data on the storage device without first decompressing the data. Furthermore, the '381 patent does not contemplate decompressing all compressed data read from memory associated with a disk drive controller before that data is provided to a system bus. Instead, the '381 patent discusses transferring over a system bus compressed data read from a disk drive in compressed form without first decompressing that data. Therefore, according to the '381 patent, the host system must be capable of compressing and decompressing data. In the case of storing raw uncompressed data to a storage device using interchangeable media, for example, removable disk cartridges, the '381 patent requires that all hosts must have the ability to decompress data and to differentiate compressed from uncompressed data.
For the above-stated reasons, it would be desirable to provide a method and apparatus for improving the apparent bandwidth of memory used in connection with a memory controller. In addition, it would be advantageous to provide a method and apparatus capable of increasing the apparent bandwidth of memory as compared to the bandwidth exhibited by such memory when used without the method and apparatus of the present invention, and that did not require modifications to the host system. Furthermore, it would be advantageous to provide a method and apparatus for increasing the apparent bandwidth of memory that could be implemented within an application specific integrated circuit (ASIC) or as part of the firmware of a microprocessor. In addition, it would be advantageous to provide such a method and apparatus that are reliable in operation and that are relatively inexpensive to implement.